In VLSI technology, multi-levels of metallization on silicon are used to increase the circuit density. Each layer of conducting lines are isolated by dielectric, for example, fused quartz, silicon dioxide or polymer layers, and the conducting lines on separate layers are interconnected by vias or studs. The composite structure must experience temperature excursion due to processing integration. Because of the difference in the thermal expansion coefficient between the interconnect metal, typically aluminum or aluminum-silicon, or aluminum-copper alloys, and the dielectric, thermal stress is induced. The thermal stress is a driving force for the low yield and low reliability of the device structure. The thermal stress can cause rupture, cracking or voiding by metal creep or deformation and results in electrical failures of opens and shorts.
One example of thermal stress would be a composite of aluminum lines on fused quartz first annealed at 400.degree. C., and then cooled to 85.degree. C. 400.degree. C. is a typical processing temperature that the interconnect metallization may experience and 85.degree. C. is a typical operating temperature of the interconnect metallization in the field. Since 400.degree. C. is a relatively high temperature for atomic motion to occur in aluminum, the aluminum is relaxed and free of stress. The aluminum upon cooling, wants to shrink and is prevented from shrinking by the fused quartz, therefore, the aluminum after cooling is under tension. Since pure aluminum and fused quartz have respectively linear thermal expansion coefficient of 25.times.10.sup.-6 /.degree.C., and 0.5.times.10.sup.-6 /.degree.C., the linear thermal strain between a temperature excursion of 400.degree. C. to 85.degree. C. is expressed in equation 1. ##EQU1## In equation 1, l is the total length of the metallization, .delta.l is the change in length of the metallization, .DELTA..alpha. is the difference of the thermal expansion coefficient for the two materials, and .DELTA.T is the temperature excursion in degrees Celsius.
In a metal solid, provided that shear motion by dislocation slip can occur, the elastic limit is about 0.2% strain, i.e., beyond that plastic deformation takes place.
In a publication by S. K. Groothuis, "Stress related failures causing open metallization", Rome Air Development Center Technical Report, RADC-TR-88-8 (1988), it was reported that VLSI metallization failures occur due to thermal stress between aluminum and SiO.sub.2.
In certain semiconductor devices manufactured by a major manufacturer, void formation in aluminum studs was a prime reliability problem. In FIG. 1A, a cross-sectional view of a mis-aligned aluminum stud 10 on a contact 12 is shown-formed in opening 11 of fused quartz 18. Contact 12 is in ohmic contact with semiconductor region 22 in substrate 24 which may be, for example, silicon. Metallization layer 21 may be of titanium and is formed in opening 11 over a portion of contact 12 and insulation layer 23 of silicon nitride. Layer 23 is formed over layer 25 of silicon dioxide, which in turn is formed over substrate 24. A layer 28 of chronium is formed above layer 21 in opening 11. Due to the mis-alignment, a narrow neck 14 is formed above the contact 12 neighboring the mouse hole 15. Under thermal stress a void 16 can grow across narrow neck 14 resulting in an open 17. The strain in the stud 10 is large due the fact that it is surrounded by quartz 18 which functions as an insulator. While improvement of the alignment of stud 10 to contact 12 will increase device lifetime, the key failures is due to the thermal stress in the metallization interconnects, for example, stud 10 and aluminum metallization lead 20. There is therefore a recognized need to reduce the thermal stress by providing a better match of the thermal expansion coefficient of the dielectric and the interconnect metallization.
Certain alloys have been formulated for the electrical industry which have various selected thermal expansion coefficients, for example, KOVAR, a trademark of Westinghouse Electric Corp., and INVAR, a trademark of Imphy S.A., French company.
In U.S. Pat. No. 2,877,147 which issued Mar. 10, 1959 to C. D. Thurmond, a description is given of alloyed connections to semiconductor bodies which contain, as a minor ingredient, the same basic semiconductor material as the body.
In U.S. Pat. No. 3,222,630 which issued on Dec. 7, 1965 to L. V. Gorman, aluminum-germanium alloys in the eutectic range for use as contact materials to semiconductor materials is described. A semiconductor body may have a contact material comprising an alloy containing 52-56% by weight germanium with the remainder aluminum. A gold lead wire may be pressed against the contact material causing the gold lead wire to alloy with the germanium in the contact material.
U.S. Pat. No. 3,620,837 which issued on Nov. 16, 1971 to J. Leff et al., a method is described for improving the reliability of aluminum and/or aluminum alloy lands on semiconductor integrated circuits by vapor depositing aluminum or an aluminum alloy onto a semiconductor substrate which is at a temperature between 320.degree. and 570.degree. C. The total thickness of the deposited aluminum or aluminum alloy is between 5,000 and 25,000. .ANG..
In U.S. Pat. No. 3,925,808 which issued on Dec. 9, 1975 to P. Rai-Choudhury, a silicon semiconductor device and, in particular, a high power silicon semiconductor device is described with stress-free electrodes. An electrode is formed at at least one major surface of a silicon body of a given impurity region with a solder material selected from the group consisting of aluminum, aluminum-silicon alloy, aluminum-geranium alloy, and germanium doped to&gt;about 1.times.10.sup.19 atoms/cm.sup.3 therethrough. The solder material is contacted with a degenerate silicon electrode having an impurity concentration therethrough&gt;about 1.times.10.sup.19 atoms/cm.sup.3 and preferably&gt;1.times.10.sup.20 atoms/cm.sup.3. By this arrangement, the silicon body can be mounted on and bonded to the electrode forming an ohmic contact without short circuiting the device. The assembly is heated preferably to a temperature greater than 675.degree. C. in a hydrogen atmosphere to alloy the electrode to the silicon body through a solder layer formed from the solder material. Preferably, the solder material is a silicon eutectic alloy, e.g., aluminum-11.7% by weight silicon, so that the silicon of the solder layer is obtained primarily from the solder material.
In U.S. Pat. No. 4,672,740 which issued on Jun. 16, 1987 to K. Shirai et al., a semiconductor device is described having contact windows between an aluminum or aluminum-alloy wiring layer and a diffused region in the semiconductor substrate. The contacts are formed by using a barrier film of a refractory metal silicide, for example molybdenum silicide, between the wiring layer and the diffused region. The wiring layer may be an aluminum-silicon alloy (1% silicon) deposited to a thickness of approximately 1 .mu.m.